cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 1 / 9 mtb110p10f 3 cyste k product specification p - channel enhancement mode power mosfet mtb110p10f3 features ? low gate charge ? simple drive requirement ? repetitive avalanche rated ? fast switching characteristic ? rohs compliant package symbol outline o rdering inf ormation device package shipping mtb110p10f3 - 0 - t7 - s t o - 263 (pb - free lead plating and rohs compliant package) 8 00 pcs / tape & reel mtb110p10f3 to - 2 63 g gate d drain s source bv dss - 100v i d @ v gs = - 10v - 23a r dson(typ) @ v gs = - 10v, i d = - 11a 80 m r dson(typ) @ v gs = - 4.5v, i d = - 8a 93m g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t7 : 800 pcs / tape & reel, 13 reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 2 / 9 mtb110p10f 3 cyste k product specification absolu te maximum ratings (t c =25 ? c , unless otherwise noted ) parameter symbol limits unit drain - sour c e voltage v ds - 100 v gate - source voltage v gs 20 continuous drain current @ t c =25 ? c , v gs = - 10v i d - 23 a continuous drain curren t @ t c =100 ? c , v gs = - 10v - 16 pulsed drain current (note 3) i dm - 76 continuous drain current @ t a =25 ? c , v gs =10v (note 2) i dsm - 3.0 continuous drain current @ t a =70 ? c , v gs =10v (note 2) - 2.4 avalanche current (note 3) i as - 11 avalanche energy @ l=7.1mh, i d = - 11a, r g =25 (note 2) e as 430 mj repetitive avalanche energy@ l=0.1mh (note 3) e ar 14 power dissipation t c =25 c (note 1) p d 140 w t c =100 c (note 1) 70 power dissipation t a =25 c (note 2) p dsm 2 w t a =70 c (note 2) 1.3 operating junction and storage temperature tj, tstg - 55~+1 75 ? c thermal data parameter symbol value unit thermal resistance, junction - to - case, max r th,j - c 1.1 ? c /w thermal resistance, junction - to - ambient, max (note 1 ) 62 ? c /w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction - to - case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr - 4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low freque ncy and low duty cycles to keep initial t j =25 c. 4. the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 5 . the r ja is the sum of thermal resistance from junction to case r j c and case to ambient.
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 3 / 9 mtb110p10f 3 cyste k product specification characteristics (t c =25 ? symbol min. typ. max. unit test cond itions static bv dss - 100 - - v v gs = 0v , i d = - 250 a ? bv dss / ? tj - - 0.09 - v/ c reference to 25 c, i d = - 250 a v gs(th) - 1.0 - - 2.5 v v ds = v gs , i d = - 250 a g fs - 19 - s v ds = - 10v , i d = - 11a i gss - - 100 n a v gs = 20v i dss - - - 1 a v ds = - 100v, v gs =0v - - - 2 5 v ds = - 80v, v gs =0v, tj=125 ? c *r ds ( on ) - 80 110 m v gs = - 10v , i d = - 11a - 93 125 v gs = - 4.5v , i d = - 8a dynamic *qg - 30.6 - nc i d = - 11a, v ds = - 80v, v gs = - 10v *qgs - 3.8 - *qgd - 9.3 - *t d(on) - 9.0 - ns v ds = - 50v, i d = - 11a, v gs = - 10v, r g =5.1 *tr - 1 8.2 - *t d(off) - 69.8 - *t f - 73.2 - ciss - 1726 - pf v gs =0v, v ds = - 25v, f=1mhz co ss - 104 - crss - 71 - rg - 11 - f=1mhz source - drain diode *i s - - - 23 a *i sm - - - 76 *v sd - - 0.84 - 1.3 v i s = - 11a, v gs =0v *trr - 25.3 - ns i f = - 11a, v gs =0v, di/dt=100a/ s *qrr - 33.4 - nc *pulse test : pulse width ? 3 0 0s, duty cycle ? 2%
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 4 / 9 mtb110p10f 3 cyste k product specification typical characteristics typical output characteristics 0 10 20 30 40 50 0 2 4 6 8 10 - v ds , drain-source voltage(v) - i d , drain current(a) - 10v -9v -8v -7v -6v -5v v gs =-3v v gs =-2.5v v gs =-4v v gs =-3.5v brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) -bv dss , normalized drain-source breakdown voltage i d = - 250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 100 - i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs = -3 v v gs = -4.5 v v gs = - 10v v gs =-2v v gs =-2.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 4 8 12 16 20 - i dr , reverse drain current(a) - v sd , source-drain voltage(v) tj=25 c tj=150 c static drain-source on-state resistance vs gate-source voltage 0 50 100 150 200 250 300 350 400 450 500 0 2 4 6 8 10 - v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =-11a drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) r ds(on) , normalized static drain- source on-state resistance v gs =-10v, i d =-11a r ds(on) @tj=25c : 80m typ.
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 5 / 9 mtb110p10f 3 cyste k product specification typical characteristics (cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 - v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature( c) - v g s(th) , normalized threshold voltage i d = - 250 a i d =-1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 - i d , drain current(a) g fs , forward transfer admittance(s) v ds =-10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 total gate charge---qg(nc) - v gs , gate-source voltage(v) i d =-11a v ds =-80v v ds =-50v v ds =-20v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 - v ds , drain-source voltage(v) - i d , drain current(a) dc 10ms 100ms 1ms 100 s 10 s r ds(on) limit t c =25c, tj=175c, v gs =10v,r jc =1.1c/w single pulse maximum drain current vs case temperature 0 5 10 15 20 25 25 50 75 100 125 150 175 200 t c , case temperature( c) - i d , maximum drain current(a) v gs =10v, r jc =1.1c/w
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 6 / 9 mtb110p10f 3 cyste k product specification typical chara cteristics (cont.) typical transfer characteristics 0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 10 -v gs , gate-source voltage(v) -i d , drain current (a) v ds =-10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) peak transient power (w) t j(max) =175c t c =25c jc = 1.1 c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.1 c/w
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 7 / 9 mtb110p10f 3 cyste k product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 8 / 9 mtb110p10f 3 cyste k product specification recommended wave soldering condition product peak temperature soldering time pb - free devices 260 +0/ - 5 ? c 5 +1/ - 1 seconds recommended temperature profile for ir reflow profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (tsmax to tp) 3 ? c /second max. 3 ? c /second max . preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 ? c 150 ? c 60 - 120 seconds 150 ? c 200 ? c 60 - 180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 ? c 60 - 150 seconds 217 ? c 60 - 150 seconds peak temperature(t p ) 240 +0/ - 5 ? c 260 +0/ - 5 ? c time within 5 ? c of actual peak temperature(tp) 10 - 30 seconds 20 - 40 seconds ramp down rate 6 ? c /second max. 6 ? c /second max. time 25 ? c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of th e package, measured on the package body surface.
cystech electronics corp. spec. no. : c 968f3 issued date : 20 14 . 08 . 05 revised date : page no. : 9 / 9 mtb110p10f 3 cyste k product specification to - 263 dimension *: typical dim inches millimeters dim inches millimeters min. max. min. max. min. max. min. max. a 0.3800 0.4050 9.65 10.29 i 0.0500 0.0700 1.27 1.78 b 0.3300 0.3700 8.38 9.40 j - * 0.1000 - * 2.54 c - 0.0550 - 1.40 k 0.0450 0.0550 1.14 1.40 d 0.5750 0.6250 14.61 15.88 l 0.0200 0.0390 0.51 0.99 e 0.1600 0.1900 4.06 4.83 ? 1 - - 6 ? 8 ? f 0.0450 0.0550 1.14 1.40 ? 2 - - 6 ? 8 ? g 0.0900 0.1100 2.29 2.79 ? 3 - - 0 ? 5 ? h 0.0180 0.0290 0. 46 0.74 notes : 1. controlling dimension : millimeters. 2 . maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing met hod, please contact your local cystek sales office. material : ? ? mold compound : epoxy resin family, flammability solid burning class:ul94v - 0 . important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cyste k . ? cyste k reserves the right to make changes to its products without notice. ? cyste k semiconductor products are not warranted to be suitable for use in life - support applications, or systems. ? cyste k assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. style : pin 1. gate 2. drain 3. source 3 - lead plastic surface mounted package cystek package code : f3 marking : b110 p10 device name date code a b c d 1 2 3 k l j g h f e 2 ? 1 ? 2 ? 3 i
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